All over again, the signaling of replay is delayed for the replay stage When the Check out is performed prior to the replay phase for your instruction.

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1. An equipment comprising: a primary scoreboard operating as a difficulty scoreboard to scoreboard Guidelines for problem; a next scoreboard working as a replay scoreboard to scoreboard Guidance that have handed a replay phase in the pipeline; plus a Handle circuit coupled to the 1st scoreboard and the 2nd scoreboard, wherein the Manage circuit is configured to update the 1st scoreboard to point that a write is pending for a first location register of a first instruction in reaction to issuing the first instruction into the pipeline, and whereby the Command circuit is configured to update the 2nd scoreboard to indicate that the produce is pending for the first spot sign-up in response to the primary instruction passing the replay stage with the pipeline, wherein the Manage circuit, in reaction to some replay of a second instruction by examining operands of the 2nd instruction versus the next scoreboard, is configured to repeat contents of the next scoreboard to the main scoreboard.

The bit corresponding to the destination register on the floating point instruction might be set within the FP Madd Uncooked replay scoreboard 46F in response on the instruction passing the replay stage. The little bit can be cleared in equally scoreboards nine clock cycles before the floating issue instruction updates its outcome. The number of clock cycles may possibly fluctuate in other embodiments. Generally, the amount of clock cycles is chosen to align the sign-up file examine (RR) stage to the insert operand with the floating stage multiply-increase instruction Along with the stage at which result details is forwarded to the prior floating position instruction. The amount may count on the number of pipeline phases in between The problem phase and also the sign up file browse (RR) stage for that include operand from the floating place multiply-include pipeline (which includes each levels) and the quantity of stages involving the result forwarding stage as well as produce phase on the floating issue pipeline.

In response into a replay or redirect on account of department misprediction, The problem Command circuit 42 may well duplicate the contents in the integer replay scoreboard 44B towards the integer difficulty scoreboard 44A. On this style, the updates to the integer situation scoreboard 44A because of Guidelines which were issued but canceled due to replay could be deleted. Additionally, the point out from the scoreboard for Recommendations which were not canceled (These outside of the replay stage) may very well be retained. Similarly, in response to an exception, The problem Management circuit 42 could copy the contents of the integer graduation scoreboard 44C to both the integer replay scoreboard 44B and to the integer difficulty scoreboard 44A.

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The floating point load instruction contains a decreased latency than other floating level Guidance (5 clock cycles from problem to sign-up file create (Wr) in the situation of the cache strike). To account for WAW dependencies concerning a floating stage instruction as well as a subsequent floating point load, the FP Load WAW challenge scoreboard 46I could be used as well as FP Load WAW replay scoreboard 46J could be used to Recuperate from replay/redirect and exceptions. The bit comparable to the desired destination register of the floating issue instruction could possibly be established during the FP Load WAW problem scoreboard 46I in reaction to issuing the instruction. The bit corresponding to the spot sign-up of the floating stage instruction could be set inside the FP Load WAW replay scoreboard 46J in reaction on the instruction passing the replay phase.

If a floating stage load instruction is a pass up (conclusion block 110), The problem Manage click here circuit 42 sets the little bit for that destination register in the floating issue load from the FP Uncooked Load replay scoreboard 46A (block 112). If a floating position load skip is passing the graduation stage (final decision block 114), the issue Manage circuit 42 sets the bit for that desired destination register on the floating point load from the FP Uncooked Load graduation scoreboard 46B (block 114). In response to issuing a floating position instruction into one of the floating position pipelines (decision block 118), the issue Management circuit forty two sets the bit for your spot register of the floating point instruction in Each individual from the FP EXE Uncooked challenge scoreboard 46C, the FP Madd RAW situation scoreboard 46E, the FP EXE WAW challenge scoreboard 46G, as well as FP Load WAW difficulty scoreboard 46I (block one hundred twenty).

In one embodiment, The problem Management circuit forty two may perhaps carry out a method for energy discounts if replays are taking place as a result of dependencies on load misses in the data cache 30. Generally, The problem Manage circuit forty two may well detect if a replay is happening because of a load miss out on, and may inhibit challenge of Directions if replay is happening because of the load miss out on until fill knowledge is returned. Other triggers of replay may very well be A part of a variety of embodiments. By way of example, as described above, a person embodiment on the processor 10 works by using multiple execute cycle to perform integer multiplies (e.g. two clock cycles might be utilized). In such an embodiment, the integer multiply could be tracked inside the integer scoreboards 44. In other embodiments, the one cause of replay will be the dependency around the load skip and thus the detection of a replay may well lead to the inhibiting of instruction concern.

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11. The equipment as recited in assert one wherein the Management circuit is configured to update the primary scoreboard and the 2nd scoreboard to indicate which the generate will not be pending to the 1st spot sign-up at a first predetermined clock cycle previous to the initial instruction creating the 1st destination register.

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